Non-volatile memory can retain stored information without the continual requirement of short-interval refresh operations; for these reasons, non-volatile memory can potentially save power and extend the functionality and usability of portable devices. To reduce cost, certain forms of non-volatile memory have been designed for programming or erasing in units of minimum size (“pages” or “blocks”). A typical limitation of these designs, however, is that it often takes a relatively long time to program or erase data, often on the order of hundreds of microseconds or longer. Because devices based on these designs typically cannot be used for other purposes while such a state change operation is in progress, a bottleneck can be created.
The conventional state change of a page or block of such memory is introduced with reference to a timing diagram 101 seen in FIG. 1. The processing includes a number of cycles, each termed a “program-verify cycle” or “PV cycle” (this term is used for both programming and erasing operations, despite the presence of the word “program” in the term). With each cycle, high voltage circuitry on-board the memory device (that is, several times a reference voltage provided to the chip, or approximately 20-30 Volts DC) is used to apply one or more voltage “pulses” to cells within a page or block to urge them toward a desired logic state (e.g., contents of a logic “1” in the case of “erasing” or “resetting,” or one of two alternative binary values, logic “1” or logic “0,” in the case of a typical “programming” or “setting” operation). Several such pulses are often used, because an incremental approach helps avoid “over-programming” (i.e., to apply the smallest voltage possible for the smallest amount of time, and so avoid high electric fields which can damage cells). Each individual pulse is usually part of a discrete state change cycle (i.e., a “program phase” of the PV cycle), with the memory device performing a verification of memory contents after each pulse (a “verify phase” of the PV cycle) to detect deviations within the cells of the block or page from desired state or states. If any cells in the page or block have not assumed the correct state, a further state change cycle is then applied, up to a number “N” of such cycles. In some designs, the voltage can be increased between cycles in an attempt to provide additional impetus. Not all designs use this latter technique. As indicated by FIG. 1, the complete state change operation for a particular page or block, often consisting of as many as 10-20 PV cycles, can take hundreds of microseconds or longer (represented by a time 103), effectively preventing the memory device from being used for other operations. For example, if it is desired to program a second page “B” as depicted in FIG. 1, a controlling device (e.g., a memory controller) must typically wait a minimum time 103 before it can do anything.
Thus, a need exists for ways of reducing the bottleneck and thereby enhancing the potential application of non-volatile memory devices. The present invention satisfies these needs and provides further, related advantages.